1. Field of the Invention
This invention relates to an analog-to-digital conversion method in high-density multilevel non-volatile memory devices, being of the type wherein a reading operation is performed on a multilevel memory cell, comprising a floating gate transistor with drain and source terminals, by applying predetermined bias voltage values to its drain and source terminals while its drain terminal is applied a predetermined current value, and by measuring the value of its gate voltage.
The invention further relates to a device implementing the method.
2. Description of the Related Art
Known are multilevel memory devices which can store plural logic values in a single memory cell. Such devices are in the form of integrated electronic circuits, which have attained a sufficient degree of reliability to allow their manufacture in large volumes for a variety of technical and commercial applications.
Multilevel memory devices are in high demand on the market of semiconductor-integrated electronic devices for the reason that they afford an information storage density which is at least twice as high as that of two-level memory devices, for the same technology and area requirements.
In the light of these considerations, any efforts to develop memory devices that can store a larger number of bits per memory cell are well warranted.
However, this goal clashes with technical problems posed by the very increase in the number of bits stored in a single cell, and by the handling thereof. Also, multilevel memory devices are expected to perform comparably with two-level memory devices, and especially to exhibit the same synchronous and asynchronous access times, same read and program parallelism, and same program and erase speeds.
To best appreciate all the aspects of this invention, the main electrical characteristics of a multilevel memory device will be reviewed briefly herein below.
A different programmed state of a memory cell reflects in a different value of its threshold voltage Vth.
With a two-level cell, there can only be two values, respectively corresponding to a logic xe2x80x9c0xe2x80x9d and a logic xe2x80x9c1xe2x80x9d. In this operational context, the amount of information that can be stored is of one bit per cell.
By contrast, a multilevel memory cell can store a larger number of bits than one. From the electrical standpoint, this means that the threshold voltage can have more than two values. The amount of information that can be stored in a single multilevel cell increases according to the following relation:
n bits/cell=log2(n values of Vth). 
From a physical standpoint, the ability to alter the threshold voltage Vth, and hence to program the multilevel memory cell, is afforded by the floating gate structure of the transistor which comprises the memory cell. The gate region is isolated in D.C. but accessible through charge injection processes of the Channel Hot Electrons and/or the Fowler-Nordheim Tunneling Effect types.
These processes, when suitably controlled, allow the amount of charge which is caught within the floating gate to be modulated, so that the effect of the latter on the value of the threshold voltage Vth can be altered.
A major problem of multilevel memory handling is that, as the number of the possible programmed states increases, the gap xcex94Vth between consecutive threshold voltage values decreases dramatically, according to the following relation:
xcex94Vth=xcex94Vtot/(n values of Vth). 
In fact, reliability factors forbid an expansion of the overall gap xcex94Vtot to accommodate the various programmed states beyond 5 to 6V. Furthermore, in view of all the process xe2x80x9cspreadsxe2x80x9d likely to occur, the variations in the operational conditions of the memory device (i.e., supply voltage, temperature, etc.), and the accuracy of the programming processes, the threshold voltage levels are bound to vary somewhat on either sides of their nominal values. It is customary to indicate this situation in terms of different xe2x80x9cdistributionsxe2x80x9d of the individual programmed states, rather than xe2x80x9cexact valuesxe2x80x9d thereof.
This particular aspect reflects in further narrowing of the nominal gap xcex94Vth between adiacent programmed states, which requires the accuracy of the circuits concerned with reading the logic information from the cells to be augmented proportionally.
For example, with sixteen-level memory cells, that is cells capable of storing four bits each, the above considerations lead to estimating the actual gap xcex94Vth at around 200 mV. For typical current gains of the memory cells, on the order of 10 xcexcA/V, the current difference between adjacent programmed states would be about 2 xcexcA.
Under conditions such as these, the read circuitry that incorporates the sense amplifiers has great difficulty to discriminate between programmed states of the cell, unless the read time can be considerably extended, which would lead to degraded performance of the device as regards memory access time.
It should be further added that current-mode sensing schemes may xe2x80x9cdisturbxe2x80x9d the programmed state of an addressed cell and result in progressive alteration of its threshold voltage Vth. This phenomenon is recognized as xe2x80x9cread disturbxe2x80x9d in the relevant literature. In fact, current-mode reading is achieved by maintaining, on the terminals of the addressed cell, definite bias conditions which are the same for all the cells and, therefore, unrelated to the cell programmed states. These conditions may be, for example: Vg=6 V; Vdrain=1 V; and Vsource=0 V.
In this way, the information contained in the addressed cell can be derived from the cell drain current.
However, these reading bias conditions lead to electric fields being developed between the conduction channel and the floating gate, which fields are the stronger the smaller is the value of the threshold voltage Vth. Unfortunately, these electric fields are sufficiently strong to significantly raise the probability of charge being injected into the floating gate. This phenomenon results in re-programming, as harmful as it is undesired, of the addressed cell and may strike unevenly, since its effectiveness is proportional to the difference between the read voltage Vg and the threshold voltage Vth.
The net outcome of all this is a progressive reduction of the gap xcex94Vth separating adjacent programmed states, with a consequent loss of reliability which will be the more significant the smaller the gep xcex94Vth and the larger the number of bits stored in each cell.
It should be considered, moreover, that current-mode reading is affected by the source resistance introducing non-linearity, to the point that the informational contents of a selected cell may be read erroneously.
In the light of the above considerations, the need of a circuit architecture which were effective to read from memory cells having n levels, e.g. sixteen levels, and ensured a read time of less than 100 ns, affording a memory access time on the order of 150 ns, can be fully appreciated.
It also appears from the foregoing considerations that the xe2x80x9ccurrentxe2x80x9d mode reading approach is inadequate to meet the above requirement.
However, another method of reading the informational contents of a memory cell has been proposed in the art.
This prior approach is a xe2x80x9cvoltagexe2x80x9d mode sensing method which allows the information stored in the cell to be retrieved by determining the cell threshold voltage Vth, or a voltage proportional thereto, usually the gate voltage Vg. In principle, the xe2x80x9cvoltagexe2x80x9d sensing method consists of forcing a suitable drain current (Iref), concurrently with predetermined bias conditions, on the drain and source terminals of the cell (e.g., Vdrain=1 V and Vsource=0 V). These being the conditions for operation, the gate voltage produced by the cell, Vsenseout, is extracted.
This voltage Vsenseout becomes a function of the threshold voltage Vth once the drain current Iref and the current gain Gm of the cell are set, according to the following relation:
Vg=Vsenseout=Vth+Gn*Iref. 
This value univocally represents the programmed state of the cell.
Shown schematically in FIG. 1 of the accompanying drawings is an example of a sense amplifier 1 which is negative-feedback looped to the gate terminal G of a cell 2, so as to control its voltage Vg to the value whereat the drain current of the cell 2 exactly equals the reference current Iref.
It is noteworthy that the degree of reliability would benefit considerably from a circuit like that shown FIG. 1 because of the voltage Vg produced at the gate terminal G of the cell 2 exceeding the threshold voltage Vth by a constant and reasonably small amount (equal to Gm*Iref).
For example, with a value of Gm equal to 20 xcexcA/V and a reference current Iref of 12 xcexcA, a threshold voltage Vth of 600 mV can be obtained.
It follows that any read disturbance on the addressed cell would be quite minor, besides being uniform, i.e. unrelated to the programmed state of the cell.
Thus, xe2x80x9cvoltagexe2x80x9d reading can suppress the xe2x80x9cread disturbxe2x80x9d effect that deteriorates the gap xcex94Vth separating adjacent programmed states. This is the approach described in European Patent Application No. 99830071.9 by the Applicant and the Applicant""s U.S. Pat. No. 6,034,888.
A gate voltage Vg which has been extracted by this technique must then be converted into a set of bits (e.g., four bits) representing the informational contents from the cell being read.
Assume, by way of example, a sixteen-level programmed cell (four bits per cell), and that a voltage-mode reading approach be used. The four bits which represent the informational contents of the selected cell can be obtained from the gate voltage Vg by means of an A/D conversion device. Of the most commonly used types of A/D conversions, the xe2x80x9cflashxe2x80x9d type, so called because of its high rate of conversion, is more suitable.
Fifteen comparators are needed to implement this technique, which comparators should be compensated for offset and capable of comparing a voltage difference of 50 mV, representing the theoretical difference between the gate voltage Vg of a programmed level and its nearest comparative voltage, while also taking temperature variations into account.
FIG. 2 shows a schematic example of a conventional flash A/D converter.
As previously mentioned, a major advantage of this technique resides in its conversion rate, due to its convert time being substantially the compare time of a single comparator.
However, there are also disadvantageous aspects to take into account, as follows:
ample occupation of circuit area; for example, the total area of the converter is equal to the area of one comparator multiplied by fifteen, that is by the number (nxe2x88x921) of levels;
high power consumption, due to the need of a large number of comparators; also, using fast comparators makes consumption worse, since a higher speed is accompanied by higher consumption, and vice versa.
With the comparators being required to compare higher voltages than the external supply voltage VDD, the comparators must be supplied higher voltages than VDD.
Such voltages are usually generated by charge pump voltage boosters inside the integrated circuit. Charge pump circuits have low efficiencies (less than 40%) and, accordingly, several charge pump stages must be provided to power these comparators, resulting in increased area occupation.
Another A/D conversion technique consists of using a single comparator to compare serially, for each level, the gate and reference voltages, carrying out one comparison after another. This technique does require less area and involve lower consumption, but is evidently made slower by that n steps are necessary to obtain the output bits. The total convert time is n*Tc, where Tc is the compare time of one comparator (e.g., n=15; Tc=10 nsxe2x86x92Ttot=150 ns), clearly resulting in degraded memory access time.
There are further A/D conversion techniques, known as combined techniques, such as dichotomic, successive approximation, serial-parallel techniques, or else.
Summarized in the table herein below are the advantages and disadvantages of all these A/D conversion techniques.
None of the solutions currently used in the state of the art provides a converter capable of combining the converting performance of the flash method with the minimal area requirements and reduced consumption of the serial method.
An embodiment of this invention provides an analog-to-digital conversion method for high-density multilevel non-volatile memory devices, as well as a conversion device implementing the method, with such functional and structural features as to exhibit short convert time, reduced circuit area requirements, and reduced power consumption.
In other words, the circuit performing the analog-to-digital conversion is to occupy a minimal area on the semiconductor and exhibit very low consumption. Above all, conversion time should be sufficiently short not to degrade the memory access time.
One embodiment of this invention provides a two steps conversion: a first step wherein the most significant bits MSB are converted within a predetermined time window, and a second step wherein the least significant bit LSB are converted within a period of time corresponding to the best solutions of the prior art.
The invention relates to an analog-to-digital conversion method in high-density multilevel non-volatile memory devices, comprising the following steps:
reading a multilevel memory cell, comprising a floating gate transistor with drain and source terminals, by applying predetermined bias voltage values to its drain and source terminals while its drain terminal receives a predetermined current value;
measuring the value of the cell gate voltage;
converting the most significant bits (MSB) contained in the memory cell;
converting the least significant bits (LSB) contained in the memory cell.
The invention further relates to an analog-to-digital conversion device incorporated in high-density multilevel non-volatile memory devices, of the type used for reading the contents of a multilevel memory cell comprising a floating gate transistor with drain and source terminals, and further comprising a plurality of voltage comparators, each having a first input coupled to the floating gate and a second input maintained at a corresponding reference voltage value, the comparator outputs being connected to a logic block for extracting the most significant bits of the cell.
The features and advantages of the conversion method and device according to this invention will be apparent from the following description of embodiments thereof, given by way of non-limiting examples with reference to the accompanying drawings.